In data transmission and many analogue and digital systems, accurate and stable delay elements are often necessary for various purposes such as the generation of predetermined width pulses, clock synchronization, clock multiplication and clock/data recovery. In traditional phase locked loop (PLL) or other mixed analog-digital approaches, the clock rate of a controlled oscillator or the time delay value of a delay element can be obtained by applying an analog voltage or current as the control signal to its voltage controlled oscillator locked to a reference oscillator. This control signal is often a filtered or smoothed output from a phase detector, frequency range controller, a timing detection circuit, or a combined control signal from several detectors. The analog nature of the control signal enables a continuous, stepless tuning of the controlled frequency or time delay value, however, the high loop gain due to high frequency or high data rate operations, makes the operation very sensitive to noise. Performance optimization becomes difficult especially when integration with very large scale high speed digital functions is necessary, since digital switching operations tends to induce a large amount of switching noise.
An all-digital phase locked loop, based on use of time delay elements, can eliminate these concerns. By using a plurality of small delay elements in series to construct time delays, time delay values can be obtained having a "resolution" determined by the delay value of the individual element. The delay element could be a standard integrated circuit inverter device. However, the delay of the inverters are not fixed and will be variable due to process variations, temperature change, and power supply noise. Therefore, where a constant, accurate delay is required, such as in most of the precise applications mentioned above, the standard inverter is not adequate.
As CMOS and other processing technologies provide more density of devices, long strings of cascaded inverters of small delay can be obtained at lower and lower cost and the inverters can be used as the basic high resolution unit delay element. In addition, all-digital solutions are becoming attractive to replace many more applications which are implemented now in analog technique or mixed analog-digital schemes.
In applications where a plurality of unit delay cells are used to form various timing bases, a need exists for a general detection scheme which can provide the time delay value of the basic delay cell on-the-fly in a digital format, i.e., in real time, and which employs only standard logic cells such that it can be readily integrated with the digital functions that require accurate delay or delay regulation.